danke
ich habe nämlich den verdacht,das die beiden sich irgendwie blockieren.ich poste mal die daten.vieleicht könnt ihr was damit anfangen
General Information :
ROW-0 (RAS 6, RAS 11) : 512 (Double Bank)
ROW-1 (RAS 4, RAS 11) : 256 (Single Bank)
ROW-2 : Empty
Information SPD EEPROM (ROW-0) :
Manufacturer : MCI Computer
Part Number : MDT512M PC333 CL2.
Serial Number : 55072007
Type : DDR-SDRAM PC2700 (166 MHz) - [DDR-333]
Size : 512 MB (2 rows, 4 banks)
Module Buffered : No
Module Registered : No
Width : 64-bit
Error Correction Capability : No
Max. Burst Length : 8
Refresh : Reduced (.5x)7.8 µs, Self Refresh
Voltage : SSTL 2.5v
Manufacture : Week 5 of 2004
Supported Frequencies : 133 MHz, 166 MHz
CAS Latency (tCL) : 2 clocks @133 MHz, 2.5 clocks @166 MHz
RAS to CAS (tRCD) : 3 clocks @133 MHz, 3 clocks @166 MHz
RAS Precharge (tRP) : 3 clocks @133 MHz, 3 clocks @166 MHz
Cycle Time (tRAS) : 6 clocks @133 MHz, 7 clocks @166 MHz
Information SPD EEPROM (ROW-1) :
Manufacturer : MCI Computer
Part Number : MDT256M PC400 CL2.
Serial Number : 5B052008
Type : DDR-SDRAM PC3200 (200 MHz) - [DDR-400]
Size : 256 MB (1 rows, 4 banks)
Module Buffered : No
Module Registered : No
Width : 64-bit
Error Correction Capability : No
Max. Burst Length : 8
Refresh : Reduced (.5x)7.8 µs, Self Refresh
Voltage : SSTL 2.5v
Manufacture : Week 3 of 2005
Supported Frequencies : 166 MHz, 200 MHz
CAS Latency (tCL) : 2 clocks @166 MHz, 2.5 clocks @200 MHz
RAS to CAS (tRCD) : 3 clocks @166 MHz, 3 clocks @200 MHz
RAS Precharge (tRP) : 3 clocks @166 MHz, 3 clocks @200 MHz
Cycle Time (tRAS) : 7 clocks @166 MHz, 8 clocks @200 MHz
Memory Controller Information :
Memory Controller : Standard, FPM, EDO, Parity, ECC, SIMM
Number of connectors : 3
Max. Module Size : 128 MB
Max. Memory Size : 384 MB
Supported Speed : 70ns, 60ns
Supported Voltages : 3.3v
Error Detection Method : 32-bit ECC
Error Correction Capability : Single Bit
Current/Supported Interleave : 1-way/1-way
